# Semiconductors

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Category: Technology
Slides: 32
Updated: 2026-05-21T00:19:14.844Z
Tags: technology, semiconductors

## Summary

From Sand to Silicon: The Invisible Engine of Modernity Key sections include: Semiconductors; What Is a Semiconductor?; Band Theory of Solids; Intrinsic vs. Extrinsic; The P-N Junction; The Transistor Revolution; MOSFET: The Workhorse; Moore's Law; Silicon Wafer Production; Photolithography.

## Slide Outline

1. Semiconductors
2. What Is a Semiconductor?
3. Band Theory of Solids
4. Intrinsic vs. Extrinsic
5. The P-N Junction
6. The Transistor Revolution
7. MOSFET: The Workhorse
8. Moore's Law
9. Silicon Wafer Production
10. Photolithography
11. EUV Lithography
12. Fabrication Process Flow
13. Transistor Architecture Evolution
14. Memory Technologies
15. The Foundry Model
16. The Semiconductor Supply Chain
17. Geopolitics of Chips
18. TSMC: The World's Most Important Company
19. Chip Design Flow
20. Advanced Packaging
21. Power and Performance
22. Semiconductor Materials Beyond Silicon
23. AI and the Semiconductor Boom
24. Quantum Computing and Semiconductors
25. Key Industry Metrics
26. Semiconductor Economics
27. Environmental Impact
28. Emerging Paradigms
29. The Workforce Challenge
30. Future Roadmap: 2025-2035
31. Key Takeaways
32. Further Reading

## Slide Transcript

### Slide 1: Semiconductors

- From Sand to Silicon: The Invisible Engine of Modernity
- Trillions of transistors are manufactured each year -- more than any other human-made object in history. These crystalline slivers of silicon underpin a $600 billion global industry and form the substrate on which modern civilization computes, communicates, and creates.
- This deck traces the physics, manufacturing, economics, and geopolitics of the semiconductor revolution.

### Slide 2: What Is a Semiconductor?

- A semiconductor is a material whose electrical conductivity falls between that of a conductor (like copper) and an insulator (like glass). The most common semiconductor is silicon (Si), element 14, which has four valence electrons enabling covalent bonding into a diamond cubic crystal lattice.
- At absolute zero, pure silicon is an insulator. As temperature rises or impurities are introduced (doping), free charge carriers appear, making controlled conduction possible -- the foundation of every electronic device.

### Slide 3: Band Theory of Solids

- Energy Bands
- Valence band: highest occupied energy levels at 0 K
- Conduction band: lowest unoccupied levels where electrons move freely
- Band gap (Eg): the forbidden energy range between them
- Silicon's band gap: 1.12 eV at 300 K
- Material Classification
- Conductors: overlapping bands, Eg = 0
- Semiconductors: small gap (0.1-4 eV)
- Insulators: large gap (>4 eV, e.g. diamond = 5.5 eV)
- Temperature and photons can excite electrons across the gap

### Slide 4: Intrinsic vs. Extrinsic

- Intrinsic
- Pure semiconductor. Carrier concentration (~1.5x10^10 /cm^3 in Si at 300K) depends only on temperature. Equal numbers of electrons and holes.
- N-Type (Extrinsic)
- Doped with Group V elements (P, As, Sb). Extra electron per dopant atom. Majority carriers: electrons. Donor level just below conduction band.
- P-Type (Extrinsic)
- Doped with Group III elements (B, Ga, In). One fewer electron creates a "hole." Majority carriers: holes. Acceptor level just above valence band.

### Slide 5: The P-N Junction

- When P-type and N-type regions meet, diffusion creates a depletion zone -- a thin insulating layer devoid of free carriers. This built-in electric field (~0.7V in silicon) is the basis of diodes, solar cells, and LEDs.
- Forward bias: external voltage shrinks depletion zone, current flows
- Reverse bias: external voltage widens depletion zone, blocks current
- Breakdown: sufficiently high reverse voltage causes avalanche (Zener effect at ~5V or less)
- The junction capacitance varies with voltage -- basis of varactor diodes

### Slide 6: The Transistor Revolution

- 1947
- Bardeen, Brattain, and Shockley demonstrate the point-contact transistor at Bell Labs. They share the 1956 Nobel Prize in Physics.
- 1954
- Texas Instruments produces the first commercial silicon transistor (replacing fragile germanium), enabling mass production.
- 1958-59
- Jack Kilby (TI) and Robert Noyce (Fairchild) independently invent the integrated circuit -- multiple transistors on a single chip.
- 1963
- Frank Wanlass at Fairchild patents CMOS -- complementary N and P transistors that only draw power when switching.

### Slide 7: MOSFET: The Workhorse

- The Metal-Oxide-Semiconductor Field-Effect Transistor is the most manufactured device in human history. Over 13 sextillion (1.3x10^22) MOSFETs have been produced since 1960.
- How It Works
- Gate voltage creates electric field through oxide layer
- Field inverts channel region, creating conductive path
- Current flows from source to drain only when gate is "on"
- Acts as a voltage-controlled switch
- Key Parameters
- Threshold voltage (Vth): ~0.3-0.7V in modern nodes
- Channel length: defines the "node" (e.g., 5nm, 3nm)
- Gate oxide thickness: down to ~1nm (a few atomic layers)
- Subthreshold slope: ideally 60mV/decade at 300K

### Slide 8: Moore's Law

- In 1965, Gordon Moore observed that transistor density doubles approximately every two years. This "law" -- really an observation and self-fulfilling industry roadmap -- held for over five decades.
- 10 um
- Intel 4004 (1971) -- 2,300 transistors
- 350 nm
- Pentium Pro (1995) -- 5.5M transistors
- 65 nm
- Core 2 (2006) -- 291M transistors
- 7 nm
- Zen 2 (2019) -- 3.9B transistors
- 3 nm
- Apple M3 (2023) -- 25B transistors
- 2 nm
- Expected 2025 -- >50B transistors

### Slide 9: Silicon Wafer Production

- It all starts with sand (SiO2). The Siemens process and Czochralski method transform raw silica into 99.9999999% pure single-crystal silicon ingots -- nine nines purity.
- Reduction: SiO2 + C -> Si + CO2 in arc furnace (metallurgical-grade, 98%)
- Purification: Si + HCl -> trichlorosilane, then distillation and reduction with H2
- Crystal growth: Czochralski method pulls single-crystal boule from melt at 1,414C
- Slicing: Diamond wire saws cut 300mm wafers ~775um thick
- Polishing: Chemical-mechanical planarization (CMP) achieves atomic-level flatness

### Slide 10: Photolithography

- The pattern-transfer step that defines circuit features. A light-sensitive photoresist is exposed through a mask (reticle), then developed to reveal the pattern for etching or deposition.
- Mercury lamp (g-line 436nm) dominated through the 1980s
- Deep UV (DUV): 248nm KrF and 193nm ArF excimer lasers, 1990s-2010s
- Immersion lithography: water between lens and wafer improves resolution (2004+)
- Multi-patterning: SADP/SAQP to print below diffraction limit
- EUV (13.5nm): deployed at 7nm node and below, using tin-droplet plasma source

### Slide 11: EUV Lithography

- Extreme Ultraviolet Lithography is arguably the most complex machine ever built. ASML's NXE/EXE systems cost $150-380 million each and took 30+ years of R&D.
- Light Source
- 50,000 tin droplets/second hit by CO2 laser pulse, creating plasma that emits 13.5nm photons. Only ~6% of light is usable.
- Optics
- All-reflective (no lenses work at 13.5nm). Multilayer Mo/Si mirrors with
- Vacuum
- Entire optical path operates in near-total vacuum since air absorbs EUV. Hydrogen gas protects mirror surfaces from tin debris.

### Slide 12: Fabrication Process Flow

- A modern chip requires 80+ lithography layers and 1,000+ processing steps over 3-4 months. The major categories:
- Front-End-of-Line (FEOL)
- Well implantation (doping substrate)
- Gate oxide growth (atomic layer deposition)
- Gate patterning (poly-Si or high-k metal gate)
- Source/drain implantation
- Spacer and contact formation
- Back-End-of-Line (BEOL)
- Contact metallization (tungsten plugs)
- Copper interconnect layers (10-15 metal levels)
- Dielectric deposition (low-k materials)
- Chemical-mechanical polishing between layers
- Final passivation and pad opening

### Slide 13: Transistor Architecture Evolution

- Planar (1960-2011)
- Flat MOSFET with gate on top of channel. Gate control weakens as channel length shrinks below 30nm due to short-channel effects.
- FinFET (2011-2024)
- Channel rises as a vertical "fin" wrapped by gate on 3 sides. Better electrostatic control. Introduced by Intel at 22nm, industry-wide from 14nm.
- Gate-All-Around (2024+)
- Horizontal nanosheets/nanowires completely surrounded by gate. Samsung (3nm GAA, 2022), Intel (20A/18A RibbonFET). Ultimate short-channel control.
- CFET (2027+?)
- Complementary FET: N and P transistors stacked vertically, sharing a footprint. Could double density without shrinking features.

### Slide 14: Memory Technologies

- SRAM
- 6-transistor cell. Fastest, most power-hungry. Used for CPU caches. No refresh needed. ~0.5ns access.
- DRAM
- 1 transistor + 1 capacitor. Requires periodic refresh (64ms). Main memory standard. ~10ns access. $3-5/GB.
- NAND Flash
- Floating-gate/charge-trap cells stacked vertically (200+ layers). Non-volatile. ~100us read. SSDs, phones. $0.05/GB.
- Emerging
- MRAM (magnetic), ReRAM (resistive), PCM (phase-change). Potential to combine speed of SRAM with density of Flash.

### Slide 15: The Foundry Model

- In 1987, Morris Chang founded TSMC on a radical idea: a company that only manufactures chips designed by others. This "fabless-foundry" model transformed the industry.
- Fabless Companies
- Design chips, outsource manufacturing. AMD, Nvidia, Qualcomm, Apple, Broadcom, MediaTek. Lower capital requirements enable startup innovation.
- Foundries
- TSMC (~60% market share), Samsung Foundry (~12%), GlobalFoundries, SMIC, UMC. TSMC alone spends $30B+/year on capex.
- IDMs
- Integrated Device Manufacturers design and fabricate: Intel, Samsung, TI, Infineon. Increasingly rare model due to fab costs exceeding $20B.

### Slide 16: The Semiconductor Supply Chain

- No single country can produce an advanced chip alone. The supply chain is perhaps the most globally interdependent in any industry.
- StageKey PlayersGeography
- EDA SoftwareSynopsys, Cadence, Siemens EDAUSA
- IP CoresARM, Imagination, CEVAUK, USA
- DesignApple, Nvidia, QualcommUSA, global
- LithographyASML (monopoly on EUV)Netherlands
- EquipmentApplied Materials, Lam, Tokyo ElectronUSA, Japan
- MaterialsShin-Etsu, SUMCO, JSRJapan
- FabricationTSMC, Samsung, IntelTaiwan, Korea, USA
- PackagingASE, Amkor, TSMC (CoWoS)Taiwan, Korea

### Slide 17: Geopolitics of Chips

- Semiconductors have become a focal point of US-China rivalry and global economic security. Taiwan produces ~90% of advanced chips (
- US CHIPS Act (2022): $52.7B in subsidies for domestic fab construction
- US export controls (Oct 2022): block China from advanced EUV tools and AI chips
- EU Chips Act: EUR43B target to reach 20% global production by 2030
- Japan: $13B+ in subsidies, TSMC fab in Kumamoto (operational 2024)
- China: $47B+ in Big Fund I & II, but remains 5+ years behind on leading edge
- TSMC Arizona: $65B investment for 3 fabs, first production 2025

### Slide 18: TSMC: The World's Most Important Company

- Taiwan Semiconductor Manufacturing Company fabricates chips for Apple, Nvidia, AMD, Qualcomm, and hundreds more. A disruption at TSMC would halt the global economy.
- ~60%
- Global foundry market share
- ~90%
- Share of advanced node (
- $87B
- Revenue (2024)
- 14,000
- 300mm wafer starts per day
- 73,000+
- Employees worldwide
- $30B+
- Annual capex investment

### Slide 19: Chip Design Flow

- Designing a modern SoC takes 2-4 years and hundreds of engineers. The design flow is a cascade of abstraction:
- Architecture specification: define ISA, microarchitecture, block diagram
- RTL design: write hardware in Verilog/SystemVerilog (millions of lines)
- Verification: simulate, formal prove, emulate (60-70% of effort)
- Synthesis: convert RTL to gate-level netlist (standard cells)
- Place and route: position millions of cells, connect with metal wires
- Timing closure: iterate until all paths meet frequency target
- Physical verification: DRC, LVS, antenna checks
- Tapeout: final GDS-II file sent to foundry (~1 TB of data)

### Slide 20: Advanced Packaging

- As 2D scaling slows, packaging innovation enables "More than Moore" -- combining multiple chiplets into one package.
- 2.5D (Interposer)
- Chiplets sit side-by-side on a silicon interposer with through-silicon vias. TSMC CoWoS. Used in Nvidia H100, AMD MI300.
- 3D Stacking
- Chips bonded face-to-face or stacked with TSVs. AMD 3D V-Cache adds 64MB SRAM atop a CCD. HBM stacks DRAM 8-12 layers high.
- Chiplet Architecture
- Disaggregate SoC into smaller dies connected via UCIe or proprietary links. Better yields, mix nodes, modular design. AMD Zen uses ~13 chiplets.

### Slide 21: Power and Performance

- Dennard scaling (power density stays constant as transistors shrink) broke down around 2006. Modern chips face a "power wall."
- Dynamic Power
- P = alpha * C * V^2 * f. Reduce voltage (but leakage rises). Lower capacitance (smaller transistors). Clock gating reduces activity factor (alpha).
- Static Power (Leakage)
- Subthreshold leakage grows exponentially as Vth drops. Gate leakage reduced by high-k dielectrics (Intel 45nm, 2007). Can be 30-50% of total power in mobile chips.
- "The free lunch is over. Clock speeds plateaued around 4-5 GHz in 2004. Performance gains now come from parallelism and specialization."
- -- Herb Sutter, "The Free Lunch Is Over" (2005)

### Slide 22: Semiconductor Materials Beyond Silicon

- Gallium Arsenide (GaAs)
- Higher electron mobility than Si. Used in RF amplifiers, 5G front-ends, satellite communications. More expensive, harder to process.
- Gallium Nitride (GaN)
- Wide bandgap (3.4 eV). Handles high voltages and temperatures. Power supplies, EV chargers, radar. Growing rapidly in power electronics.
- Silicon Carbide (SiC)
- 4H-SiC bandgap: 3.26 eV. Excels at 600-1700V. EV powertrains (Tesla, BYD), industrial drives, solar inverters. Wolfspeed, STMicro, onsemi.
- Indium Phosphide (InP)
- Highest electron velocity of any common semiconductor. Fiber-optic transceivers, 100+ GHz circuits, photonic integrated circuits.

### Slide 23: AI and the Semiconductor Boom

- Generative AI has created unprecedented demand for advanced compute. Training a single frontier model can require $100M+ of GPU time.
- $47B
- Nvidia data center revenue (FY2025)
- 208B
- Transistors in Nvidia B200 GPU
- 1.8 TB/s
- HBM3E memory bandwidth per GPU
- The AI chip market is projected to exceed $300B by 2030. Custom ASICs (Google TPU, Amazon Trainium, Microsoft Maia) are challenging GPU dominance.

### Slide 24: Quantum Computing and Semiconductors

- Quantum computers require new semiconductor physics but build on existing fabrication knowledge.
- Superconducting qubits (IBM, Google): Josephson junctions fabricated on silicon, operated at 15 millikelvin
- Spin qubits (Intel): Single electrons trapped in silicon quantum dots. Compatible with CMOS fab
- Trapped ions (IonQ, Quantinuum): Semiconductor-fabricated chip traps, MEMS-like structures
- Photonic (PsiQuantum, Xanadu): Silicon photonics waveguides and detectors
- Topological (Microsoft): Semiconductor nanowires with superconducting contacts
- Error correction overhead means millions of physical qubits needed -- a manufacturing challenge

### Slide 25: Key Industry Metrics

- MetricValue (2024-25)
- Global semiconductor revenue~$620 billion
- Wafers shipped (300mm equiv.)~15 million per quarter
- Leading edge node3nm (TSMC N3E), transitioning to 2nm
- Largest single chipCerebras WSE-3: 4 trillion transistors, 46,225 mm^2
- Smallest feature printed~8nm half-pitch (EUV single-pattern)
- Highest transistor density>300 MTr/mm^2 (TSMC N2)
- Most expensive fabTSMC Fab 20 (Arizona): ~$65B total investment
- Industry R&D spend~$90B/year combined

### Slide 26: Semiconductor Economics

- Chip manufacturing is the most capital-intensive industry on Earth. The economics drive consolidation.
- Cost Escalation
- 1990s fab: ~$1B
- 2010s fab (28nm): ~$5B
- 2020s fab (3nm): ~$20B
- 2025+ fab (2nm): ~$28B
- Single EUV mask set: ~$10-20M
- Yield & Profitability
- Yield at launch: often 50-70% for complex designs
- Mature yield: 95%+ after 12-18 months
- Wafer cost (3nm): ~$20,000 per wafer
- TSMC gross margin: ~55%
- Only 3 companies can produce at

### Slide 27: Environmental Impact

- Semiconductor manufacturing is resource-intensive. A single fab consumes water and energy at city scale.
- Water
- A leading-edge fab uses 30,000-50,000 tons of ultrapure water per day. TSMC consumed 87.5M tons in 2023 -- 7.5% of Taiwan's industrial water.
- Energy
- TSMC consumed 24.8 TWh in 2023 (~6% of Taiwan's electricity). A single EUV scanner draws 1.5 MW. Industry targets 100% renewable by 2040.
- Chemicals
- PFAs ("forever chemicals") used in etching and cleaning. Industry faces regulatory pressure. SF6 and NF3 are potent greenhouse gases (17,000-23,000x CO2).

### Slide 28: Emerging Paradigms

- Neuromorphic Computing
- Chips that mimic brain architecture. Intel Loihi 2, IBM NorthPole. Event-driven, massively parallel, ultra-low power for edge AI.
- In-Memory Computing
- Process data where it's stored, avoiding the von Neumann bottleneck. Analog compute in RRAM/PCM arrays for matrix multiplication.
- Photonic Computing
- Use light for data movement and computation. Silicon photonics for interconnects. Optical neural networks for inference at speed of light.
- RISC-V Open Architecture
- Open-source ISA challenging ARM/x86 duopoly. No license fees. China investing heavily. Growing in embedded, reaching into datacenter (Ventana, Tenstorrent).

### Slide 29: The Workforce Challenge

- The industry faces a critical talent shortage as demand surges and experienced engineers retire.
- US needs 100,000+ additional semiconductor workers by 2030 (SIA estimate)
- Average age of TSMC fab engineer: rising steadily, limited pipeline from universities
- PhD programs in semiconductor physics shrunk 50% since 2000 in the US
- CHIPS Act allocates $200M for workforce development programs
- Competition for talent between Intel, TSMC Arizona, Samsung Taylor, Micron Boise
- Cross-training from adjacent fields: materials science, chemical engineering, physics

### Slide 30: Future Roadmap: 2025-2035

- 2025
- TSMC N2 (2nm nanosheet GAA) enters production. High-NA EUV (0.55 NA) enters HVM at Intel. Backside power delivery (BSPDN) debuts.
- 2027
- A14 (1.4nm equivalent). CFET prototyping. 3D DRAM development. UCIe 2.0 standard enables universal chiplet interop.
- 2030
- Sub-1nm equivalent nodes via novel materials (2D channels: MoS2, WS2). Trillion-transistor packages. Carbon nanotube FETs in labs.
- 2035
- Atomistic limits of silicon. Molecular electronics, spintronics, or quantum systems may supplement CMOS. Biology-inspired computation.

### Slide 31: Key Takeaways

- Physics Enables
- Quantum mechanics governs everything at the nanoscale. Band theory, tunneling, and electrostatics define what is possible.
- Manufacturing Is Moat
- Only 3 companies can produce leading-edge chips. The barriers to entry exceed $100B and decades of know-how.
- Geopolitics Is Destiny
- Semiconductor supply chains are the most concentrated in any strategic industry. National security and economic competitiveness depend on chip access.
- Innovation Continues
- New architectures, materials, packaging, and computing paradigms ensure the semiconductor revolution has decades of runway ahead.
- The atom is the new transistor. The transistor is the new atom. The cycle continues.

### Slide 32: Further Reading

- "Chip War" by Chris Miller (2022) -- definitive history of semiconductor geopolitics
- IEEE International Electron Devices Meeting (IEDM) proceedings -- cutting-edge device research
- TSMC Technology Symposium papers -- annual manufacturing roadmap
- Semiconductor Engineering (semiengineering.com) -- daily industry news
- "The Chip" by T.R. Reid -- the invention of the integrated circuit
- "Physics of Semiconductor Devices" by S.M. Sze -- authoritative textbook
- IRDS (International Roadmap for Devices and Systems) -- consensus industry forecast
- SEMI World Fab Forecast -- global fab construction tracker
- -- End --


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